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January 2007
HYB18T512400BF HYB18T512800BF HYB18T512160BF
512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products
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Internet Data Sheet
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512400BF, HYB18T512800BF Revision History: 2007-01, Rev. 1.05 Page All All 32 Subjects (major changes since last revision) Qimonda update Adapted internet edition added AL 5 and 6 and Rtt 50 ohms
Previous Version: 2005-11, Rev. 1.04
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03292006-YBYM-WG0Z
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.1
* * *
Features
* * * * * * * * * * * * * Posted CAS by programmable additive latency for better command and data bus efficiency Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality. Auto-Precharge operation for read and write bursts Auto-Refresh, Self-Refresh and power saving Power-Down modes Average Refresh Period 7.8 s at a TCASE lower than 85 C, 3.9 s between 85 C and 95 C Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting Full and reduced Strength Data-Output Drivers 1kB page size for x4 & x8, 2kB page size for x16 Packages: P-TFBGA-60 for x4 & x8 components PTFBGA-84 for x16 components RoHS Compliant Products1) All Speed grades faster than DDR400 comply with DDR400 timing specifications when run at a clock rate of 200 MHz.
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: 1.8 V 0.1 V Power Supply 1.8 V 0.1 V (SSTL_18) compatible I/O DRAM organizations with 4, 8 and 16 data in/outputs Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation Programmable CAS Latency: 3, 4, 5 and 6 Programmable Burst Length: 4 and 8 Differential clock inputs (CK and CK) Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. DLL aligns DQ and DQS transitions with clock DQS can be disabled for single-ended data strobe operation Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS Data masks (DM) for write data Table 1 "Performance for DDR2-800" on Page 4 Table 2 "Performance for DDR2-667" on Page 4 Table 3 "Performance for DDR2-533C" on Page 4 Table 4 "Performance for DDR2-400B" on Page 5
* * * *
* * *
* * * * *
A list of the performance tables for the various speeds can be found below
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Table 1
Performance for DDR2-800 -2.5F DDR2-800D 5-5-5 @CL6 fCK6 400 @CL5 fCK5 400 @CL4 fCK4 266 @CL3 fCK3 200 -2.5 DDR2-800E 6-6-6 400 333 266 200 15 15 45 60 Unit -- MHz MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time Table 2
tRCD tRP tRAS tRC
12.5 12.5 45 57.5
Performance for DDR2-667 -3 DDR2-667C 4-4-4 @CL5 fCK5 333 @CL4 fCK4 333 @CL3 fCK3 200 -3S DDR2-667D 5-5-5 333 266 200 15 15 45 60 Unit -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time Table 3
tRCD tRP tRAS tRC
12 12 45 57
Performance for DDR2-533C -3.7 DDR2-533C 4-4-4 @CL5 @CL4 @CL3 Unit -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
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Table 4
Performance for DDR2-400B -5 DDR2-400B 3-3-3 @CL5 @CL4 @CL3 Units -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
200 200 200 15 15 40 55
1.2
Description
Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 16-bit address bus for x4 and x8 organized components and a 15-bit address bus for x16 components is used to convey row, column and bank address information in a RAS-CAS multiplexing style. The DDR2 device operates with a 1.8 V 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in PG-TFBGA package.
The 512-Mb DDR2 DRAM is a high-speed DoubleData-Rate-Two CMOS DRAM device containing 536,870,912 bits and internally configured as a quadbank DRAM. The 512-Mb device is organized as either 32 Mbit x 4 I/O x4 banks, 16 Mbit x8 I/O x 4 banks or 8 Mbit x16 I/O x4 banks chip. These devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 to Table 4 for performance figures. The device is designed to comply with all DDR2 DRAM key features: 1. 2. 3. 4. 5. Posted CAS with additive latency, Write latency = read latency - 1, Normal and weak strength data-output driver, Off-Chip Driver (OCD) impedance adjustment On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
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Table 5
Ordering Information for RoHS compliant products Org. Speed CAS-RCD-RP Clock Latencies1)2)3) (MHz) 400 400 400 400 400 400 333 333 333 333 333 333 266 266 266 200 200 200 CAS-RCD-RP Clock Package Latencies (MHz) 4-4-4 4-4-4 4-4-4 5-5-5 5-5-5 5-5-5 3-3-3 3-3-3 3-3-3 4-4-4 4-4-4 4-4-4 3-3-3 3-3-3 3-3-3 -- -- -- 266 266 266 333 333 333 200 200 200 266 266 266 200 200 200 -- -- -- PG-TFBGA-84-8 PG-TFBGA-60-24 PG-TFBGA-60-24 PG-TFBGA-84-8 PG-TFBGA-60-24 PG-TFBGA-60-24 PG-TFBGA-84-8 PG-TFBGA-60-24 PG-TFBGA-60-24 PG-TFBGA-84-8 PG-TFBGA-60-24 PG-TFBGA-60-24 PG-TFBGA-84-8 PG-TFBGA-60-24 PG-TFBGA-60-24 PG-TFBGA-84-8 PG-TFBGA-60-24 PG-TFBGA-60-24
Product Type
HYB18T512160BF-25F x16 HYB18T512800BF-25F x8 HYB18T512400BF-25F x4 HYB18T512160BF-2.5 HYB18T512800BF-2.5 HYB18T512400BF-2.5 HYB18T512160BF-3 HYB18T512400BF-3 HYB18T512800BF-3 HYB18T512160BF-3S HYB18T512400BF-3S HYB18T512800BF-3S HYB18T512160BF-3.7 HYB18T512400BF-3.7 HYB18T512800BF-3.7 HYB18T512160BF-5 HYB18T512400BF-5 HYB18T512800BF-5 x16 x8 x4 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8
DDR2-800D 5-5-5 DDR2-800D 5-5-5 DDR2-800D 5-5-5 DDR2-800E 6-6-6 DDR2-800E 6-6-6 DDR2-800E 6-6-6 DDR2-667C 4-4-4 DDR2-667C 4-4-4 DDR2-667C 4-4-4 DDR2-667D 5-5-5 DDR2-667D 5-5-5 DDR2-667D 5-5-5 DDR2-533C 4-4-4 DDR2-533C 4-4-4 DDR2-533C 4-4-4 DDR2-400B 3-3-3 DDR2-400B 3-3-3 DDR2-400B 3-3-3
1) CAS: Column Address Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge
Note: For product nomenclature see Chapter 9 of this data sheet
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2.1
Pin Configuration
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1 for x4, Figure 2 for x8 and Figure 3 for x16. Table 6 Ball#/Pin# Pin Configuration of DDR2 SDRAM Name Pin Type I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL Clock Enable Clock Signal CK, Complementary Clock Signal CK Note: See functional description in x4/x8 organization Clock Enable Note: See functional description in x4/x8 organization Control Signals x4/x8 organizations F7 G7 F3 G8 K7 L7 K3 L8 G2 G3 RAS CAS WE CS RAS CAS WE CS BA0 BA1 I I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Chip Select Bank Address Bus 1:0 Chip Select Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Function
Clock Signals x4/x8 organizations E8 F8 F2 J8 K8 K2 CK CK CKE CK CK CKE Clock Signal CK, Complementary Clock Signal CK
Clock Signals x16 organization
Control Signals x16 organization
Address Signals x4/x8 organizations
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Table 6 Ball#/Pin# H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
Pin Configuration of DDR2 SDRAM Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC Pin Type I I I I I I I I I I I I I I I - I I - I I I I I I I I I I I I I I I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 8 Rev. 1.05, 2007-01 03292006-YBYM-WG0Z Data Signal 3:0 Address Signal 12:0, Address Signal 10/Autoprecharge Address Signal 13 Note: x4/x8 512 Mbit components Note: and x16 512 Mbit components Bank Address Bus 1:0 Function Address Signal 12:0, Address Signal 10/Autoprecharge
Address Signals x16 organization L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 C8 C2 D7 D3 BA0 BA1 NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 DQ0 DQ1 DQ2 DQ3
Data Signals x4 organizations
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 6 Ball#/Pin#
Pin Configuration of DDR2 SDRAM Name Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask Data Strobe Lower Byte Data Strobe Upper Byte Read Data Strobe Data Strobe Data Signal 15:0 Function
Data Signals x8 organization C8 C2 D7 D3 D1 D9 B1 B9 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 B7 A8 F7 E8 B3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DQS RDQS RDQS UDQS UDQS LDQS LDQS DM Data Signal 7:0
Data Signals x16 organization
Data Strobe x4/x8 organisations
Data Strobe x8 organisations
Data Strobe x16 organization
Data Mask x4/x8 organizations Data Mask x16 organization Internet Data Sheet 9 Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 6 Ball#/Pin# B3 F3
Pin Configuration of DDR2 SDRAM Name UDM LDM VDDQ VDD VSSQ VSS VREF VDDL VDD VSSDL VSS VREF VDDQ VDDL Pin Type I I PWR PWR PWR PWR AI PWR PWR PWR PWR AI PWR PWR PWR PWR PWR PWR NC Buffer Type SSTL SSTL - - - - - - - - - - - - - - - - - I/O Driver Power Supply Power Supply I/O Driver Power Supply Power Supply I/O Reference Voltage Power Supply Power Supply Power Supply Power Supply I/O Reference Voltage I/O Driver Power Supply Power Supply Power Supply I/O Driver Power Supply Power Supply Power Supply Not Connected Function Data Mask Upper/Lower Byte
Power Supplies x4/x8/x16 organizations A9,C1,C3,C7, C9 A1 A7,B2,B8,D2, D8 A3,E3 E2 E1 E9,H9,L1 E7 J1,K9 J2 E9, G1, G3, G7, G9 J1
Power Supplies x4/x8 organizations
Power Supplies x16 organization
E1, J9, M9, R1 VDD E7, F2, F8, H2, VSSQ H8 J7 J3,N1,P9 A2, B1, B9, D1, D9, G1, L3,L7, L8 G1, L3,L7, L8 VSSDL VSS NC
Not Connected x4 organizations
Not Connected x8 organization NC NC NC - - Not Connected Not Connected Not Connected x16 organization A2, E2, L1, R3, NC R7, R8 F9 K9 ODT ODT
Other Pins x4/x8 organizations I I SSTL SSTL On-Die Termination Control On-Die Termination Control Other Pins x16 organization
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Table 7 I O I/O AI PWR GND NC Table 8 SSTL LV-CMOS CMOS OD
Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation
Abbreviation
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Figure 1 Notes
Pin Configuration for x4 components, PG-TFBGA-60-24 2. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit
1. VDDL and VSSDL are power and ground for the DLL.They are isolated on the device from VDD, VDDQ, VSS, and VSSQ
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Figure 2 Notes
Pin Configuration for x8 components, PG-TFBGA-60-24 4. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device. 5. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit.
1. RDQS / RDQS are enabled by EMRS(1) command. 2. If RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads.
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Figure 3 Notes
Pin Configuration for x16 components, PG-TFBGA-84-8 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8] 3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device.
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
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2.2
512 Mbit DDR2 Addressing
Table 9
512-Mbit DDR2 Addressing 128Mb x 41) BA[1:0] 4 A10 / AP A[13:0] A11, A[9:0] 11 4 1024 (1K) 64Mb x 8 BA[1:0] 4 A10 / AP A[13:0] A[9:0] 10 8 1024 (1K) 32Mb x 16 BA[1:0] 4 A10 / AP A[12:0] A[9:0] 10 16 2048(2K) Note -- -- -- -- --
2)
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
--
3)
1) Refered to as 'org' 2) Refered to as 'colbits' 3) PageSize = 2colbits x org/8 [Bytes]
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Functional Description
Table 10 Field BA2 16
Mode Register Definition (BA[2:0] = 000B) Bits Type1) reg. addr. Description Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA2, Bank Address
BA1 BA0 A13
15 14 13
Bank Address [1] 0B BA1, Bank Address Bank Address [0] 0B BA0, Bank Address Address Bus[13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B A13, Address bit 13
PD
12
w
Active Power-Down Mode Select 0B PD, Fast exit 1B PD, Slow exit Write Recovery2) Note: All other bit combinations are illegal. 001B 010B 011B 100B 101B WR, 2 WR, 3 WR, 4 WR, 5 WR, 6
WR
[11:9] w
DLL
8
w
DLL Reset 0B DLL, No 1B DLL, Yes Test Mode 0B TM, Normal Mode 1B TM, Vendor specific test mode CAS Latency Note: All other bit combinations are illegal. 010B 011B 100B 101B 110B CL, 2 CL, 3 CL, 4 CL, 5 CL, 6 16 Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
TM
7
w
CL
[6:4]
w
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 10 Field BT 3
Mode Register Definition (BA[2:0] = 000B) Bits Type1) w Description Burst Type 0B BT, Sequential 1B BT, Interleaved Burst Length Note: All other bit combinations are illegal. 010B BL, 4 011B BL, 8
BL
[2:0]
w
1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
Table 11 Field BA2 16
Extended Mode Register Definition (BA[2:0] = 001B) Bits Type1) reg. addr. Description Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA2, Bank Address
BA1 BA0
15 14
Bank Address [1] 0B BA1, Bank Address Bank Address [0] 0B BA0, Bank Address
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Table 11 Field A13 13
Extended Mode Register Definition (BA[2:0] = 001B) Bits Type1) w Description Address Bus[13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B A13, Address bit 13
Qoff
12
Output Disable 0B QOff, Output buffers enabled 1B QOff, Output buffers disabled Read Data Strobe Output (RDQS, RDQS) 0B RDQS, Disable 1B RDQS, Enable Complement Data Strobe (DQS Output) 0B DQS, Enable 1B DQS, Disable Off-Chip Driver Calibration Program 000B OCD, OCD calibration mode exit, maintain setting 001B OCD, Drive (1) 010B OCD, Drive (0) 100B OCD, Adjust mode 111B OCD, OCD calibration default Additive Latency Note: All other bit combinations are illegal. 000B 001B 010B 011B 100B 101B AL, 0 AL, 1 AL, 2 AL, 3 AL, 4 AL, 5
RDQS
11
DQS
10
OCD [9:7] Program
AL
[5:3]
RTT
2,6
Nominal Termination Resistance of ODT 00B RTT, (ODT disabled) 01B RTT, 75 Ohm 10B RTT, 150 Ohm 11B RTT, 50 Ohm2) Off-chip Driver Impedance Control 0B DIC, Full (Driver Size = 100%) 1B DIC, Reduced DLL Enable 0B DLL, Enable 1B DLL, Disable
DIC
1
DLL
0
1) w = write only register bits 2) optional for DDR2-400/533 & 667
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Table 12 Field BA2 Bits 16
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) Type1) w Description Bank Address[2] Note: BA2 is not available on 256Mbit and 512Mbit components 0B BA2, Bank Address
BA
[15:14] w
Bank Adress[15:14] 00B BA, MRS 01B BA, EMRS(1) 10B BA, EMRS(2) 11B BA, EMRS(3): Reserved Address Bus[13:8] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B A[13:8], Address bits
A
[13:8]
w
A
7
w
Address Bus[7], adapted self refresh rate for TCase > 85C 0B A7, disable 1B A7, enable 2) Address Bus[6:4] 0B A[6:4], Address bits Address Bus[3], Duty Cycle Correction (DCC) 0B A[3], DCC disabled 1B A[3], DCC enabled Address Bus[2:0], Partial Array Self Refresh for 4 Banks3) 000B PASR0, Full Array 001B PASR1, Half Array (BA[1:0]=00, 01) 010B PASR2, Quarter Array (BA[1:0]=00) 011B PASR3, Not defined 100B PASR4, 3/4 array (BA[1:0]=01, 10, 11) 101B PASR5, Half array (BA[1:0]=10, 11) 110B PASR6, Quarter array (BA[1:0]=11) 111B PASR7, Not defined
A A
[6:4] 3
w w
Partial Self Refresh for 4 banks A [2:0] w
1) w = write only 2) When DRAM is operated at 85C TCase 95C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh mode can be entered. 3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
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Table 13 Field BA2 16
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) Bits Type1) reg.addr Description Bank Address[2] Note: BA2 is not available on 256Mbit and 512Mbit components 0B BA2, Bank Address
BA1 BA0 A
15 14 [13:0] w
Bank Adress[1] 1B BA1, Bank Address Bank Adress[0] 1B BA0, Bank Address Address Bus[13:0] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B A[13:0], Address bits
1) w = write only
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ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device Table 14 Input Pin x4 components DQ[3:0] DQS DQS DM x8 components DQ[7:0] DQS DQS RDQS RDQS DM x16 components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM X X X 0 X 0 X X X X X X 0 X 0 X X 1 1 0 X X 0 X X ODT Truth Table EMRS(1) Address Bit A10 EMRS(1) Address Bit A11 organisations (x4, x8 and x16). To activate termination of any of these pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2.
Note: X = don't care; 0 = bit set to low; 1 = bit set to high
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 15
Burst Length and Sequence Starting Address (A2 A1 A0) x00 x01 x10 x11 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Burst Length 4
8
000 001 010 011 100 101 110 111
Notes 1. Page Size and Length is a function of I/O organization: 128Mb x 4 organization (CA[9:0], CA11); Page Size = 1 KByte; Page Length = 2048 64Mb x 8 organization (CA[9:0]); Page Size = 1
KByte; Page Length = 1024 32Mb x 16 organization (CA[9:0]); Page Size = 2 KByte; Page Length = 1024 2. Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or DDR components
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
Table 16 Function
Command Truth Table CKE Previous Cycle CS RAS CAS WE BA0 A[13:11] A10 A[9:0] BA1 Current Cycle H H L H H H H H H H H X X L H L L L H L L L L L L L L L H H L H L L L L X H L L L H H H H H X X H X H L L L X H H H H L L L L H X X H X H L H H X H L L H L L H H H X X H X H X X X X -- BA X BA BA BA BA BA X X X X X Column Column Column Column X X X L H L H L H X X X X X Column -- -- --
8)
Note1)2)3)
(Extended) Mode Register Set Auto-Refresh Self-Refresh Entry Self-Refresh Exit
H H H L
BA X X X
OP Code X X X X X X X X X
4)5)
--
6) 7)
Single Bank Precharge H Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge No Operation Device Deselect Power Down Entry Power Down Exit H H H H H H H H H L
Row Address
Column -- Column -- Column -- X X X
9)
--
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 2) "X" means "H or L (but a defined logic level)". 3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register. 6) VREF must be maintained during Self Refresh operation. 7) Self Refresh Exit is asynchronous. 8) Burst reads or writes at BL = 4 cannot be terminated. 9) The Power Down Mode does not perform any refresh operations.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 17
Clock Enable (CKE) Truth Table for Synchronous Transitions Previous Cycle6) Current Cycle (N) (N-1) Command (N)2)3) Action (N) RAS, CAS, WE, CS X X Maintain Power-Down Maintain Self Refresh Note4)5)
Current State1) CKE
Power-Down Self Refresh Bank(s) Active All Banks Idle
L L L L H H H
L H L H L L L H
7)8) 9)10)11) 12) 13)14) 15)
DESELECT or NOP Power-Down Exit DESELECT or NOP Self Refresh Exit DESELECT or NOP Active Power-Down Entry DESELECT or NOP Precharge Power-Down Entry AUTOREFRESH Self Refresh Entry Refer to the Command Truth Table
--
16) 17)
Any State other H than listed above
1) 2) 3) 4) 5)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. CKE must be maintained HIGH while the device is in OCD calibration mode. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements 8) "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). 9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2xtCKE + tIH. 12) VREF must be maintained during Self Refresh operation. 13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 14) Valid commands for Self Refresh Exit are NOP and DESELCT only. 15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. 16) Self Refresh mode can only be entered from the All Banks Idle state. 17) Must be a legal command as defined in the Command Truth Table.
Table 18
Data Mask (DM) Truth Table DM L H DQs Valid X Note
1)
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
--
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
5
5.1
Electrical Characteristics
Absolute Maximum Ratings
Table 19 Symbol
Absolute Maximum Ratings Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Rating -1.0 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 Unit V V V V C Note
1)
VDD VDDQ VDDL VIN, VOUT TSTG
-- -- --
2)
Storage Temperature -55 to +100 1) When VDD and VDDQ and VDDL are less than 500mV; Vref may be equal to or less than 300mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated circuit. Table 20 Symbol TOPER DRAM Component Operating Temperature Range Parameter Operating Temperature Rating 0 to 95 Unit C Note
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
Table 21 Symbol
Recommended DC Operating Conditions (SSTL_18) Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Rating Min. Typ. 1.8 1.8 1.8 0.5 x VDDQ Max. 1.9 1.9 1.9 0.51 x VDDQ V V V V
1)
Unit
Note
VDD VDDDL VDDQ VREF VTT
1) 2) 3) 4)
1.7 1.7 1.7 0.49 x VDDQ
-- --
2)3)
4) Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. Peak to peak ac noise on VREF may not exceed 2% VREF (dc) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF.
Table 22
ODT DC Electrical Characteristics Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM Min. 60 120 40 -6.00 Nom. 75 150 50 -- Max. 90 180 60 + 6.00 Unit % Note
1)
Parameter / Condition Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Deviation of VM with respect to VDDQ / 2
1)
-- --
2)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) /(I(VIHac) - I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) - 1) x 100%
Table 23 Symbol
Input and Output Leakage Currents Parameter / Condition Input Leakage Current; any input 0 V < VIN < VDD Output Leakage Current; 0 V < VOUT < VDDQ Min. -2 -5 Max. +2 +5 Unit A A Note
1) 2)
IIL IOL
1) All other pins not under test = 0 V 2) DQ's, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
relative to the rising or falling edges of DQS crossing at
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured Table 24 Symbol
VREF. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care.
DC & AC Logic Input Levels for DDR2-667 and DDR2-800 Parameter DC input logic high DC input low AC input logic high AC input low DDR2-667, DDR2-800 Min. Max. Units
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
Table 25 Symbol
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
V V V V
VREF + 0.200
--
VREF - 0.200
DC & AC Logic Input Levels for DDR2-533 and DDR2-400 Parameter DC input logic high DC input low AC input logic high AC input low DDR2-533, DDR2-400 Min. Max. Units
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
Table 26 Symbol
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
V V V V
VREF + 0.250
--
VREF - 0.250
Single-ended AC Input Test Conditions Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum Slew Rate Value 0.5 x VDDQ 1.0 Unit V V Note
1)
VREF VSWING.MAX
SLEW
--
2)3) 1.0 V / ns 1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to VIL(ac).MAX for falling edges as shown in Figure 4 3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac)
on the negative transitions.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Figure 4 Table 27 Symbol
Single-ended AC Input Test Conditions Diagram Differential DC and AC Input and Output Logic Levels Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage Min. -0.3 0.25 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 Max. Unit -- -- V V V Note
1) 2) 3) 4)
VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac)
1) 2) 3) 4)
VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.175
0.5 x VDDQ + 0.125
5)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR- VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
Figure 5
Differential DC and AC Input and Output Logic Levels Diagram
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
Table 28 Symbol
SSTL_18 Output DC Current Drive Parameter Output Minimum Source DC Current SSTL_18 -13.4 Unit mA Note
1)2)
IOH IOL
3) Output Minimum Sink DC Current 13.4 mA 1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2) The values of IOH(dc) and IOL(dc) are based on the conditions given in and . They are used to test drive current capability to ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement. 3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Table 29 Symbol
SSTL_18 Output AC Test Conditions Parameter Minimum Required Output Pull-up Maximum Required Output Pull-down SSTL_18 Unit V V Note
1)
VOH VOL VOTR
Output Timing Measurement Reference Level V -- 1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that 335 mV must be
developed across the effectively 25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA x 45 Ohm = 603 mV).
VTT + 0.603 VTT - 0.603 0.5 x VDDQ
--
Table 30 Symbol -- -- --
OCD Default Characteristics Description Output Impedance Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Min. -- 0 0 1.5 -- -- -- 4 1.5 5.0 Nominal Max. Unit Ohms Ohms Ohms V / ns Note
1)2) 3) 4)
SOUT
Output Slew Rate 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
5)6)7)
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT-VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV. 3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage. 4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 0.75 Ohms under nominal conditions. 5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC. This is verified by design and characterization but not subject to production test. 6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ's is included in tDQSQ and tQHS specification. 7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
Table 31 Symbol CCK CDCK CI CDI CIO CDIO
Input / Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS Min. 1.0 -- 1.0 -- 2.5 -- Max. 2.0 0.25 1.75 0.25 3.5 0.5 Unit pF pF pF pF pF pF
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
5.6
Overshoot and Undershoot Specification
Table 32 Parameter
AC Overshoot / Undershoot Specification for Address and Control Pins DDR2-400 DDR2-533 DDR2-667 DDR2-800 Unit 0.9 0.9 1.00 1.00 0.9 0.9 0.80 0.80 0.9 0.9 0.80 0.80 V V V.ns V.ns
Maximum peak amplitude allowed for overshoot area 0.9 Maximum peak amplitude allowed for undershoot area 0.9 Maximum overshoot area above VDD Maximum undershoot area below VSS 1.33 1.33
Figure 6 Table 33 Parameter
AC Overshoot / Undershoot Diagram for Address and Control Pins AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins DDR2-400 DDR2-533 DDR2-667 DDR2-800 Unit 0.9 0.38 0.38 0.9 0.9 0.28 0.28 0.9 0.9 0.23 0.23 0.9 0.9 0.23 0.23 V V V.ns V.ns
Maximum peak amplitude allowed for overshoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ
Maximum peak amplitude allowed for undershoot area 0.9
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Figure 7
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
6
Specifications and Conditions
Table 34 Parameter
IDD Measurement Conditions Symbol Note
Operating Current - One bank Active - Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching.
IDD0
1)2)3)4) 5)6)
Operating Current - One bank Active - Read - Precharge IDD1 IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are floating. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching, Data bus inputs are switching. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data bus inputs are floating.
IDD2N
IDD2Q
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating. MRS A12 bit is set to "0" (Fast Power-down Exit). Active Power-Down Current IDD3P(1) All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit); Active Standby Current IDD3N All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA. Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Burst Refresh Current IDD5B tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. Distributed Refresh Current IDD5D tCK = tCK(IDD), Refresh command every tREFI = 7.8 s interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 34 Parameter
IDD Measurement Conditions Symbol Note
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current IDD7 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 2. Timing pattern: DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks) DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks) DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks) DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks) DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks) DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks) 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled.
4) 5) 6) 7) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD: see Table 35 Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7.. A = Activate, RA = Read with Auto-Precharge, D=DESELECT
7)
Table 35 Parameter LOW HIGH STABLE FLOATING
Definition for IDD Description defined as VIN VIL(ac).MAX defined as VIN VIH(ac).MIN defined as inputs are stable at a HIGH or LOW level defined as inputs are VREF = VDDQ / 2 defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes
SWITCHING
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 36
IDDSpecification for HYB18T512xxxBF
-2.5F -2.5 Max. 80 100 95 115 7 51 45 39 9 60 155 180 155 200 145 9 7 160 255 -3 Max. 75 95 90 105 7 45 40 33 9 50 130 155 130 170 140 9 7 160 252 -3S Max. 71 90 85 100 7 45 40 33 9 50 130 155 130 170 140 9 7 152 240 -3.7 Max. 65 80 75 90 7 38 35 28 9 43 110 130 110 145 130 9 7 145 230 -5 Max. 61 75 70 83 7 34 32 24 9 39 95 115 95 130 125 9 7 141 220 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x8 x16 x4/x8 x16 -- -- --
1) 2)
Unit
Note
DDR2-800D DDR2-800E DDR2-667C DDR2-667D DDR2-533C DDR2-400B Symbol Max. 84 105 100 120 7 51 45 39 9 60 155 180 155 200 145 9 7 170 265
1) MRS(12)=0 2) MRS(12)=1 3) 0 TCASE 85C.
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
-- x4/x8 x16 x4/x8 x16 --
3)
-- x4/x8 x16
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
7
7.1
Timing Characteristics
Speed Grade Definitions
This chapter contains speed grade definition, AC timing parameter and ODT tables.
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with tRAS = 40ns). List of Speed Grade Definition tables: * * * * Table 37 "Speed Grade Definition Speed Bins DDR2-800" on Page 36 Table 38 "Speed Grade Definition Speed Bins for DDR2-667" on Page 37 Table 39 "Speed Grade Definition Speed Bins for DDR2-533C" on Page 37 Table 40 "Speed Grade Definition Speed Bins for DDR2-400B" on Page 38 Speed Grade Definition Speed Bins DDR2-800 DDR2-800D -2.5F 5-5-5 Symbol @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Min. 5 3.75 2.5 2.5 45 57.5 12.5 12.5 Max. 8 8 8 8 70000 -- -- -- DDR2-800E -2.5 6-6-6 Min. 5 3.75 3 2.5 45 60 15 15 Max. 8 8 8 8 70000 -- -- -- Unit Note
Table 37
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns ns
1)2)3)4)
tCK tCK tCK tCK tRAS tRC tRCD tRP
-- -- --
5)
-- -- --
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 38
Speed Grade Definition Speed Bins for DDR2-667 DDR2-667 -3 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3 3 45 57 12 12 Max. 8 8 8 70000 -- -- -- DDR2-667 -3S 5-5-5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
-- --
5)
-- -- --
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Table 39
Speed Grade Definition Speed Bins for DDR2-533C DDR2-533 -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
-- --
5)
-- -- --
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 40
Speed Grade Definition Speed Bins for DDR2-400B DDR2-400 -5 3-3-3 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
-- --
5)
-- -- --
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
7.2
* * * *
AC Timing Parameters
List of Timing Parameters Tables. Table 41 "Timing Parameter by Speed Grade - DDR2-800" on Page 39 Table 42 "Timing Parameter by Speed Grade - DDR2-667" on Page 41 Table 43 "Timing Parameter by Speed Grade - DDR2-533" on Page 44 Table 44 "Timing Parameter by Speed Grade - DDR2-400" on Page 47 Timing Parameter by Speed Grade - DDR2-800 Symbol DDR2-800 Min. Max. +400 -- 0.55 -- 0.55 -- ps -400 2 0.45 3 0.45 WR + tRP Unit Note1)2)3)4)5)
6)
Table 41 Parameter
tAC CAS A to CAS B command period tCCD CK, CK high-level width tCH CKE minimum high and low pulse width tCKE CK, CK low-level width tCL Auto-Precharge write recovery + precharge tDAL
DQ output access time from CK / CK time Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
-- -- -- -- --
7)
tCK tCK tCK tCK tCK
ns ps ps
tIS + tCK + tIH --
125 -- 0.35 -350 0.35 -- - 0.25 50 -- 0.2 0.2 MIN. (tCL, tCH) -- 250 0.6 -- -- -- +350 -- 200 + 0.25 -- -- -- --
8)
tDH(base) tDH1(base)
-- -- -- -- --
9)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
-- -- -- -- --
10) 11)
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input)
tCK tCK
--
tDSS tHP tHZ tIH(base) tIPW
tAC.MAX
-- --
ps ps
-- --
tCK
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 41 Parameter
Timing Parameter by Speed Grade - DDR2-800 (cont'd) Symbol DDR2-800 Min. Max. -- ps ps ps 175 2 x tAC.MIN Unit Note1)2)3)4)5)
6)
Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble
tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI tRFC tRP tRPRE tRPST tRRD tRTP
-- -- -- -- -- -- --
12)13) 14) 15)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 300 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
tCK
ns -- ps s s ns ns
tHP-tQHS
-- -- -- 105
tRP
0.9 0.40 7.5 10 7.5 0.35 x tCK 0.40 15
16)
tCK tCK
ns ns ns
-- --
17)
-- -- --
18)
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command WR
tCK tCK
ns
--
19)
tWR/tCK
7.5 2 8 - AL 2
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
20) 21)
tCK tCK tCK
ns
-- -- -- --
tRFC +10
200
Exit Self-Refresh to Read command 1) VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1 V. See notes
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT.
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required. 9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 12) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 13) 0 C TCASE 85 C 14) 85 C < TCASE 95 C 15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank precharge. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
Table 42 Parameter
Timing Parameter by Speed Grade - DDR2-667 Symbol DDR2-667 Min. Max. +450 -- 0.55 -- 0.55 -- -- -- -- -- +400 -- ps -450 2 0.45 3 0.45 WR + tRP Unit Note1)2)3)4)5)
6)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW
tAC tCCD tCH tCKE tCL tDAL tDELAY
-- -- -- -- --
7)
tCK tCK tCK tCK tCK
ns ps ps
tIS + tCK + tIH
175 -- 0.35 -400 0.35
8)
DQ and DM input hold time (differential data tDH(base) strobe) DQ and DM input hold time (single ended data strobe) DQ and DM input pulse width (each input)
-- -- -- -- --
tDH1(base)
tDIPW DQS output access time from CK / CK tDQSCK DQS input low (high) pulse width (write cycle) tDQSL,H
tCK
ps
tCK
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 42 Parameter
Timing Parameter by Speed Grade - DDR2-667 (cont'd) Symbol DDR2-667 Min. Max. 240 + 0.25 -- -- -- -- ps -- - 0.25 100 -- 0.2 0.2 MIN. (tCL, tCH) -- 275 0.6 200 2 x tAC.MIN Unit Note1)2)3)4)5)
6) 9)
DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition
tDQSQ tDQSS
tCK
ps ps
-- -- -- -- --
10) 11)
DQ and DM input setup time (differential data tDS(base) strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock half period
tDS1(base) tDSH tDSS
tCK tCK
--
tHP Data-out high-impedance time from CK / CK tHZ Address and control input hold time tIH(base) Address and control input pulse width tIPW
(each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay
tAC.MAX
-- -- --
ps ps
-- -- -- -- -- -- -- -- --
12)13) 14) 15)
tCK
ps ps ps
tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI tRFC tRP tRPRE tRPST tRRD
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 340 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- --
tCK
ns -- ps s s ns ns
tHPQ - tQHS
-- -- -- 105
tRP
0.9 0.40 7.5 10 7.5 0.35 x tCK 0.40 15
16)
tCK tCK
ns ns ns
-- --
17)
-- -- --
18)
Internal Read to Precharge command delay tRTP
tWPRE tWPST tWR
WR
tCK tCK
ns
--
19)
tWR/tCK
7.5
tCK
ns
tWTR
20)
Internet Data Sheet
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 42 Parameter
Timing Parameter by Speed Grade - DDR2-667 (cont'd) Symbol DDR2-667 Min. Max. -- -- -- -- -- 2 7 - AL 2 Unit Note1)2)3)4)5)
6) 21)
Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command
tXARD tXARDS tXP tXSNR tXSRD
tCK tCK tCK
ns
-- -- -- --
tRFC +10
200
Exit Self-Refresh to Read command 1) VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1 V. See notes
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required. 9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 12) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 13) 0 C TCASE 85 C 14) 85 C < TCASE 95 C 15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank precharge. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
Internet Data Sheet
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 43 Parameter
Timing Parameter by Speed Grade - DDR2-533 Symbol DDR2-533 Min. Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- ps -500 2 0.45 3 0.45 WR + tRP Unit Note1)2)3)4)
5)6)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time
tAC tCCD tCH tCKE tCL tDAL
-- -- -- -- --
7)
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
8)
tDH(base) tDH1(base)
-- -- -- -- --
9)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
-- -- -- -- --
10) 11)
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS
tCK tCK
--
tDSS tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH
44
tAC.MAX
-- -- --
ps ps
-- -- -- -- -- -- -- --
tCK
ps ps ps
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 --
tCK
ns --
tHP -tQHS
Internet Data Sheet
Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 43 Parameter
Timing Parameter by Speed Grade - DDR2-533 (cont'd) Symbol DDR2-533 Min. Max. 400 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- -- ps s s ns ns -- -- -- 105 Unit Note1)2)3)4)
5)6)
Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble
tQHS tREFI tRFC tRP tRPRE tRPST tRRD tRTP
--
12)13) 14) 15)
tRP
0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
16)
tCK tCK
ns ns ns
-- --
17)
-- -- --
18)
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command WR
tCK tCK
ns
--
19)
tWR/tCK
7.5 2 6 - AL 2
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
20) 21)
tCK tCK tCK
ns
-- -- -- --
tRFC +10
200
Exit Self-Refresh to Read command 1) VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1 V. See notes
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required. 9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 12) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 13) 0 C TCASE 85 C 14) 85 C < TCASE 95 C 15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank precharge. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table 44 Parameter
Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2-400 Min. Max. +600 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 350 + 0.25 -- -- -- -- ps -600 2 0.45 3 0.45 WR + tRP Unit Note1)2)3)4)5)
6)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time
tAC tCCD tCH tCKE tCL tDAL
-- -- -- -- --
7)
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
275 -25 0.35 -500 0.35 -- - 0.25 150 -25 0.2 0.2 MIN. (tCL, tCH) -- 475 0.6 350 2x
8)
tDH(base) tDH1(base)
-- -- -- -- --
9)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
-- -- -- --
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Internet Data Sheet
tCK tCK
--
tDSS tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH
47
10) 11)
tAC.MAX
-- -- --
ps ps
-- -- -- -- -- -- -- --
tCK
ps ps ps
tAC.MIN tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 --
tCK
ns --
tHP -tQHS
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Table 44 Parameter
Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2-400 Min. Max. 450 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- -- ps s s ns ns -- -- -- 105 Unit Note1)2)3)4)5)
6)
Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period
tQHS tREFI tRFC
--
12)13) 14) 15)
tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B command tRRD
period Internal Read to Precharge command delay Write preamble
tRP
0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
16)
tCK tCK
ns ns ns
-- --
17)
-- -- --
18)
tRTP
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge WR
tCK tCK
ns
Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command
tWR/tCK
10 2 6 - AL 2
tCK
ns
19)
tWTR tXARD tXARDS tXP tXSNR tXSRD
20) 21)
tCK tCK tCK
ns
-- -- -- --
tRFC +10
200
Exit Self-Refresh to Read command 1) VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1 V. See notes
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required. 9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 12) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 13) 0 C TCASE 85 C 14) 85 C < TCASE 95 C 15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank precharge. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
7.3
ODT AC Electrical Characteristics
Table 45 Symbol
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Note --
1)
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
tAC.MIN tAC.MAX + 0.7 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
-- --
2)
tCK
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
-- -- --
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Table 46 Symbol
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400 Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Note --
1)
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
-- --
2)
tCK
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
-- -- --
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
8
Package Dimensions
Figure 8
Package Pinout PG-TFBGA-60
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Figure 9
Package Outline P-TFBGA-84
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
9
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Table 47 Nomenclature Fields and Examples Field Number 1 DDR2 DRAM Table 48 Field 1 2 3 4 HYB 2 18 3 T 4 512 5 16 6 7 0 8 A 9 C 10 -3.7 11
Example for
DDR2 Memory Components Description QIMONDA Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G Coding Constant SSTL_18 DDR2 256 M 512 M 1 Gb x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
5+6
Number of I/Os
40 80 160
7 8 9
Product Variations Die Revision Package, Lead-Free Status Speed Grade
0 .. 9 A B C F
10
-3 -3S -3.7 -5
11
N/A for Components
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Pin Configuration for x4 components, PG-TFBGA-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration for x8 components, PG-TFBGA-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration for x16 components, PG-TFBGA-84-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . Package Pinout PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline P-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 14 28 28 31 32 51 52
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Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Performance for DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance for DDR2-533C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance for DDR2-400B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 512-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mode Register Definition (BA[2:0] = 000B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . 19 EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . 20 ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC & AC Logic Input Levels for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC & AC Logic Input Levels for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Differential DC and AC Input and Output Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SSTL_18 Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OCD Default Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . 31 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . 31 IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 IDDSpecification for HYB18T512xxxBF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speed Grade Definition Speed Bins DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Speed Grade Definition Speed Bins for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Speed Grade Definition Speed Bins for DDR2-533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Speed Grade Definition Speed Bins for DDR2-400B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Timing Parameter by Speed Grade - DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Parameter by Speed Grade - DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 . . . . . . . . . . . . . . . . 50 ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . . 50 Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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HYB18T512xxxBF-[2.5...5] 512-Mbit Double-Data-Rate-Two SDRAM
Table of Contents
1 1.1 1.2 2 2.1 2.2 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 6 7 7.1 7.2 7.3 8 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 26 27 29 30 31 36 36 39 50
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Internet Data Sheet
56
Rev. 1.05, 2007-01 03292006-YBYM-WG0Z
Internet Data Sheet
Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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